Full bridge current driven vertical deflection output circuit in LVDMOS
Full bridge current driven vertical deflection output circuit in LVDMOS
Full bridge vertical deflection output circuit in LVDMOS
Full bridge vertical deflection output circuit in LVDMOS
18-bit buffer/line driver; non-inverting (3-State)
18-bit buffer/line driver; non-inverting (3-State)
18-bit buffer/line driver; non-inverting (3-State)
18-bit buffer/line driver; non-inverting (3-State)
18-bit buffer/line driver; non-inverting (3-State)
18-bit buffer/line driver; non-inverting (3-State)
18-bit buffer/line driver; non-inverting (3-State)
18-bit buffer/line driver; non-inverting (3-State)
18-bit buffer/line driver; non-inverting (3-State)
18-bit buffer/line driver; non-inverting (3-State)
18-bit bus interface D-type flip-flop with reset and enable (3-State)
18-bit bus interface D-type flip-flop with reset and enable (3-State)
18-bit bus interface D-type flip-flop with reset and enable (3-State)
18-bit bus interface D-type flip-flop with reset and enable (3-State)
18-bit bus interface D-type flip-flop with reset and enable (3-State)
18-bit bus interface D-type flip-flop with reset and enable (3-State)
18-bit bus interface D-type flip-flop with reset and enable (3-State)
18-bit bus interface D-type flip-flop with reset and enable (3-State)
18-bit bus interface D-type flip-flop with reset and enable (3-State)
18-bit bus interface D-type flip-flop with reset and enable (3-State)
18-bit bus interface D-type flip-flop with reset and enable (3-State)
18-bit bus-interface D-type flip-flop with reset and enable with 30Ω termination resistors (3-State)
18-bit bus-interface D-type flip-flop with reset and enable with 30Ω termination resistors (3-State)
18-bit bus-interface D-type flip-flop with reset and enable with 30Ω termination resistors (3-State)
18-bit bus-interface D-type flip-flop with reset and enable with 30Ω termination resistors (3-State)
18-bit bus-interface D-type flip-flop with reset and enable with 30Ω termination resistors (3-State)
18-bit GTL/GTL+ to LVTTL/TTL bidirectional universal translator (3-State)
18-bit GTL/GTL+ to LVTTL/TTL bidirectional universal translator (3-State)
18-bit GTL/GTL+ to LVTTL/TTL bidirectional universal translator (3-State)
18-bit universal bus driver with 5V tolerant inputs (3-State)
18-bit universal bus driver with 5V tolerant inputs (3-State)
18-bit universal bus driver with 5V tolerant inputs (3-State)
18-bit universal bus driver with 5V tolerant inputs (3-State)
18-bit registered driver with inverted register enable (3-State)
18-bit registered driver with inverted register enable (3-State)
18-bit registered driver with inverted register enable and 15 Ω termination resistors (3-State)
18-bit registered driver with inverted register enable and 15 Ω termination resistors (3-State)
18-bit universal bus transceiver with 30 Ω termination resistor; 3-state
18-bit universal bus transceiver with 30 Ω termination resistor; 3-state
18-fold ESD transient voltage suppressor
N-channel enhancement mode vertical D-MOS transistor
1GHz low voltage LNA, mixer and VCO
Low-voltage 1GHz fractional-N synthesizer
Low-voltage 1GHz fractional-N synthesizer
1K dual mode serial EEPROM